I am an Offensive Security Researcher at Intel, dedicated to pioneering security enhancements for hardware, firmware, and software systems. My core research areas include:

• Static Analysis of RTL Designs: Engineering and implementing methodologies for (security) verification of large-scale hardware designs to ensure comprehensive and effective security validation.
• Automated Security Validation: Developing and establishing automated processes to enhance the security of hardware, embedded firmware, and software, including approaches based on artificial intelligence (AI).
• Test and Debug Security: Analyzing privacy and security challenges posed by testing and debugging features and hardening secure debug architectures and their implementation.
• Supply Chain Security: Developing robust measures to safeguard the integrity of the hardware supply chain.

At Intel, I led initiatives to harden hardware and firmware security of communications systems and platforms — including 5G Base Transceiver Stations and Bluetooth/Wi-Fi chipsets. Previously, as a Platform Security Architect, I was responsible for the end-to-end security architecture of cellular modem chipsets.

Prior to joining Intel, I pursued postdoctoral research at the System Security Lab at Technische Universität Darmstadt, Germany. My work focused on the design, development, formal modeling, and security analysis of novel security architectures and cryptographic protocols. This included leveraging hardware-based security primitives such as Physically Unclonable Functions (PUFs) to enhance authentication and attestation mechanisms in embedded systems.